Spike, a RISC-V ISA Simulator
This report presents the forensic synthetic code analysis of riscv-software-src/riscv-isa-sim, a C project with 3,171 GitHub stars. SynthScan v2.0 examined 66,434 lines of code across 1916 source files, recording 349 pattern matches distributed across 3 syntactic categories. The overall adjusted score of 4.1 places this repository in the Likely human-written band.
The scanner applied 160+ deterministic lexical heuristics, multi-line block detectors, abstract syntax tree depth profilers, and a cross-file Jaccard similarity matrix to construct a statistically normalised synthetic code estimate. All matches are individually weighted by severity coefficient and contextual multiplier before summation, and the resulting headline score is temporally discounted to account for the repository's development history relative to the commercial emergence of large language model coding tooling (November 2022 onward).
Longitudinal tracking requires multiple scan runs. Once this repository is re-scanned after new commits land, this chart will visualise how the synthetic code signal evolves over time — enabling you to detect whether AI authorship is growing, stabilising, or being actively corrected by human engineers.
Classifies detected patterns by their diagnostic confidence and structural impact. CRITICAL patterns (coefficient 10) represent definitive synthetic signatures — hallucinated imports, explicit LLM attribution metadata — virtually never produced by human authors. HIGH (5) indicates strong structural tells such as cross-file repetition or cross-linguistic idioms. MEDIUM (2) covers recognisable conversational padding and AI-specific vocabulary. LOW (1) captures subtle indicators like tautological comments and generic boilerplate that require density to carry independent signal.
This horizontal bar chart decomposes the repository's raw synthetic code score by top-level directory, allowing you to pinpoint precisely which modules or components carry the highest AI authorship density. Directories with disproportionately high scores relative to their size warrant targeted manual review: concentrated AI signatures often trace back to mass-generated configuration layers, auto-ported test suites, LLM-scaffolded boilerplate classes, or entire subsystems authored under heavy copilot assistance. Use this view to prioritise your human code-review effort.
The scanner identified 349 distinct pattern matches across 3 syntactic categories. Each entry below represents a discrete location in the source code where the engine recorded a statistically significant AI authorship indicator. Expand any category row to inspect the individual file paths, line numbers, code snippets, and the lexical context (CODE, COMMENT, or STRING) in which each match was detected.
Reading the findings table: The Severity column indicates the diagnostic confidence level (CRITICAL / HIGH / MEDIUM / LOW). The Context column identifies whether the match occurred inside executable code, an inline comment, or a string literal — comment-context matches receive a ×1.5 weight because LLMs systematically over-annotate. The ⚡ bolt icon marks clustered matches: three or more patterns within a 10-line window, each receiving an additional ×1.5 density multiplier as dense clusters constitute far stronger evidence of synthetic authorship than isolated hits.
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| LOW | customext/dummy_rocc_test.c | 1 | // The following is a RISC-V program to test the functionality of the | COMMENT |
| LOW | softfloat/specialize.h | 61 | #define i8_fromPosOverflow 0x7F | COMMENT |
| LOW | softfloat/primitiveTypes.h | 61 | #ifdef LITTLEENDIAN | COMMENT |
| LOW | softfloat/primitiveTypes.h | 81 | #define indexMultiwordLoBut( total, n ) (n) | COMMENT |
| LOW | softfloat/softfloat.h | 41 | | header, "softfloat.h", be created that folds in "softfloat_types.h" and that | COMMENT |
| LOW | softfloat/platform.h | 41 | #define LITTLEENDIAN 1 | COMMENT |
| LOW | fdt/libfdt_env.h | 1 | /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ | COMMENT |
| LOW | fdt/fdt.h | 61 | #define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) | COMMENT |
| LOW | fesvr/htif.h | 1 | // See LICENSE for license details. | COMMENT |
| LOW | fesvr/context.h | 1 | #ifndef _HTIF_CONTEXT_H | COMMENT |
| LOW | fesvr/elf.h | 1 | // See LICENSE for details. | COMMENT |
| LOW | fesvr/tsi.h | 1 | #ifndef __SAI_H | COMMENT |
| LOW | fesvr/dtm.h | 1 | #ifndef _ROCKET_DTM_H | COMMENT |
| LOW | scripts/vcs-version.sh | 1 | #!/usr/bin/env bash | COMMENT |
| LOW | scripts/vcs-version.sh | 21 | # where X is the major release, Y is the minor release, Z is the number | COMMENT |
| LOW | arch_test_target/spike/model_test.h | 41 | //RVTEST_IO_WRITE_STR | COMMENT |
| LOW | riscv/zvkned_ext_macros.h | 1 | // Helper macros to help implement instructions defined as part of | COMMENT |
| LOW | riscv/zvkned_ext_macros.h | 201 | (STATE)[ 3] = (STATE)[ 7]; \ | COMMENT |
| LOW | riscv/devices.h | 1 | #ifndef _RISCV_DEVICES_H | COMMENT |
| LOW | riscv/vector_unit.h | 121 | } | COMMENT |
| LOW | riscv/entropy_source.h | 21 | static const uint32_t OPST_ES16 = 0x2 << 30; | COMMENT |
| LOW | riscv/decode_macros.h | 1 | // See LICENSE for license details. | COMMENT |
| LOW | riscv/decode_macros.h | 61 | } | COMMENT |
| LOW | riscv/decode_macros.h | 81 | #define RVC_FRS2S READ_FREG(insn.rvc_rs2s()) | COMMENT |
| LOW | riscv/decode_macros.h | 101 | // Zilsd macros | COMMENT |
| LOW | riscv/decode_macros.h | 121 | #define FRS1_D READ_FREG_D(insn.rs1()) | COMMENT |
| LOW | riscv/decode_macros.h | 161 | COMMENT | |
| LOW | riscv/decode_macros.h | 261 | #define serialize() set_pc_and_serialize(npc) | COMMENT |
| LOW | riscv/decode_macros.h | 341 | #define e128 128 // 128b elements | COMMENT |
| LOW | riscv/processor.h | 1 | // See LICENSE for license details. | COMMENT |
| LOW | riscv/zvksh_ext_macros.h | 1 | // Helper macros and functions to help implement instructions defined as part of | COMMENT |
| LOW | riscv/zvksh_ext_macros.h | 41 | #define T2 0x7A879D8A | COMMENT |
| LOW | riscv/debug_rom_defines.h | 1 | // See LICENSE file for license details. | COMMENT |
| LOW | riscv/encoding.h | 21 | #define MSTATUS_UIE _RISCV_UL(0x00000001) | COMMENT |
| LOW | riscv/encoding.h | 41 | #define MSTATUS_SDT _RISCV_UL(0x01000000) | COMMENT |
| LOW | riscv/encoding.h | 61 | #define SSTATUS_UPIE _RISCV_UL(0x00000010) | COMMENT |
| LOW | riscv/encoding.h | 81 | #define HSTATUS_VGEIN _RISCV_UL(0x0003f000) | COMMENT |
| LOW | riscv/encoding.h | 101 | #define DCSR_EBREAKVS (1<<17) | COMMENT |
| LOW | riscv/encoding.h | 121 | #define DCSR_CAUSE_HALT 5 | COMMENT |
| LOW | riscv/encoding.h | 141 | #define MCONTROL_STORE (1<<1) | COMMENT |
| LOW | riscv/encoding.h | 161 | #define MIP_SSIP (1 << IRQ_S_SOFT) | COMMENT |
| LOW | riscv/encoding.h | 181 | #define MIDELEG_FORCED_MASK MIP_HS_MASK | COMMENT |
| LOW | riscv/encoding.h | 201 | #define MENVCFGH_ADUE _RISCV_UL(0x20000000) | COMMENT |
| LOW | riscv/encoding.h | 221 | #define MSTATEEN0H_HCONTEXT _RISCV_UL(0x02000000) | COMMENT |
| LOW | riscv/encoding.h | 241 | COMMENT | |
| LOW | riscv/encoding.h | 261 | #define HENVCFG_ADUE _RISCV_ULL(0x2000000000000000) | COMMENT |
| LOW | riscv/encoding.h | 281 | COMMENT | |
| LOW | riscv/encoding.h | 301 | #define HSTATEEN0_AIA _RISCV_ULL(0x0800000000000000) | COMMENT |
| LOW | riscv/encoding.h | 321 | #define SENVCFG_PMM _RISCV_ULL(0x0000000300000000) | COMMENT |
| LOW | riscv/encoding.h | 341 | #define HVICTL_DPR _RISCV_UL(0x00000200) | COMMENT |
| LOW | riscv/encoding.h | 361 | #define SATP_MODE_OFF 0 | COMMENT |
| LOW | riscv/encoding.h | 381 | COMMENT | |
| LOW | riscv/encoding.h | 401 | #define MCTRCTL_M _RISCV_ULL(0x0000000000000004) | COMMENT |
| LOW | riscv/encoding.h | 421 | COMMENT | |
| LOW | riscv/encoding.h | 441 | COMMENT | |
| LOW | riscv/encoding.h | 461 | #define VSCTRCTL_CUSTOM _RISCV_ULL(0xF000000000000000) | COMMENT |
| LOW | riscv/encoding.h | 481 | #define IRQ_S_SOFT 1 | COMMENT |
| LOW | riscv/encoding.h | 501 | #define PTE_W 0x004 /* Write */ | COMMENT |
| LOW | riscv/encoding.h | 521 | COMMENT | |
| LOW | riscv/encoding.h | 561 | #define clear_csr(reg, bit) ({ unsigned long __tmp; \ | COMMENT |
| 280 more matches not shown… | ||||
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| MEDIUM | scripts/vcs-version.sh | 2 | #========================================================================= | COMMENT |
| MEDIUM | scripts/vcs-version.sh | 4 | #========================================================================= | COMMENT |
| MEDIUM | scripts/vcs-version.sh | 48 | #------------------------------------------------------------------------- | COMMENT |
| MEDIUM | scripts/vcs-version.sh | 50 | #------------------------------------------------------------------------- | COMMENT |
| MEDIUM | scripts/vcs-version.sh | 66 | #------------------------------------------------------------------------- | COMMENT |
| MEDIUM | scripts/vcs-version.sh | 68 | #------------------------------------------------------------------------- | COMMENT |
| MEDIUM⚡ | scripts/vcs-version.sh | 84 | #------------------------------------------------------------------------- | COMMENT |
| MEDIUM⚡ | scripts/vcs-version.sh | 86 | #------------------------------------------------------------------------- | COMMENT |
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| MEDIUM⚡ | scripts/vcs-version.sh | 85 | # Create the version string | COMMENT |