Yosys Open SYnthesis Suite
This report presents the forensic synthetic code analysis of YosysHQ/yosys, a C++ project with 4,641 GitHub stars. SynthScan v2.0 examined 64,238 lines of code across 467 source files, recording 293 pattern matches distributed across 14 syntactic categories. The overall adjusted score of 5.8 places this repository in the Low AI signal band.
The scanner applied 160+ deterministic lexical heuristics, multi-line block detectors, abstract syntax tree depth profilers, and a cross-file Jaccard similarity matrix to construct a statistically normalised synthetic code estimate. All matches are individually weighted by severity coefficient and contextual multiplier before summation, and the resulting headline score is temporally discounted to account for the repository's development history relative to the commercial emergence of large language model coding tooling (November 2022 onward).
Longitudinal tracking requires multiple scan runs. Once this repository is re-scanned after new commits land, this chart will visualise how the synthetic code signal evolves over time — enabling you to detect whether AI authorship is growing, stabilising, or being actively corrected by human engineers.
Classifies detected patterns by their diagnostic confidence and structural impact. CRITICAL patterns (coefficient 10) represent definitive synthetic signatures — hallucinated imports, explicit LLM attribution metadata — virtually never produced by human authors. HIGH (5) indicates strong structural tells such as cross-file repetition or cross-linguistic idioms. MEDIUM (2) covers recognisable conversational padding and AI-specific vocabulary. LOW (1) captures subtle indicators like tautological comments and generic boilerplate that require density to carry independent signal.
This horizontal bar chart decomposes the repository's raw synthetic code score by top-level directory, allowing you to pinpoint precisely which modules or components carry the highest AI authorship density. Directories with disproportionately high scores relative to their size warrant targeted manual review: concentrated AI signatures often trace back to mass-generated configuration layers, auto-ported test suites, LLM-scaffolded boilerplate classes, or entire subsystems authored under heavy copilot assistance. Use this view to prioritise your human code-review effort.
The scanner identified 293 distinct pattern matches across 14 syntactic categories. Each entry below represents a discrete location in the source code where the engine recorded a statistically significant AI authorship indicator. Expand any category row to inspect the individual file paths, line numbers, code snippets, and the lexical context (CODE, COMMENT, or STRING) in which each match was detected.
Reading the findings table: The Severity column indicates the diagnostic confidence level (CRITICAL / HIGH / MEDIUM / LOW). The Context column identifies whether the match occurred inside executable code, an inline comment, or a string literal — comment-context matches receive a ×1.5 weight because LLMs systematically over-annotate. The ⚡ bolt icon marks clustered matches: three or more patterns within a 10-line window, each receiving an additional ×1.5 density multiplier as dense clusters constitute far stronger evidence of synthetic authorship than isolated hits.
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| LOW | .pre-commit-config.yaml | 1 | # To use: | COMMENT |
| LOW | techlibs/xilinx/cells_xtra.py | 21 | # - UG613 (Spartan 3A) | COMMENT |
| LOW | techlibs/xilinx/cells_xtra.py | 41 | # Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}), | COMMENT |
| LOW | techlibs/xilinx/cells_xtra.py | 61 | # Cell('RAM64X8SW', port_attrs={'WCLK': ['clkbuf_sink']}), | COMMENT |
| LOW | techlibs/xilinx/cells_xtra.py | 81 | # Cell('OR2L'), | COMMENT |
| LOW | techlibs/xilinx/cells_xtra.py | 201 | # Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3 | COMMENT |
| LOW | techlibs/xilinx/cells_xtra.py | 381 | Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 21 | class State(Enum): | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 41 | #Cell("FD1P3DX"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 61 | #Cell("IBPU"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 81 | #Cell("MUX41"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 101 | #Cell("OR3"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 121 | #Cell("XOR3"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 181 | ]), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 201 | #Cell("FD1P3BX"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 221 | #Cell("FL1P3IY"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 241 | #Cell("INV"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 261 | #Cell("MULT2"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 281 | #Cell("OFS1P3IX"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 301 | #Cell("VHI"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 321 | Cell("PDPW8KC"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 341 | #Cell("ODDRDQSX1A"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 361 | ]), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 381 | #Cell("FD1P3BX"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 401 | #Cell("FL1P3IY"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 421 | #Cell("INV"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 441 | #Cell("MULT2"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 461 | #Cell("OFS1P3IX"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 481 | #Cell("VHI"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 501 | Cell("PDPW8KC"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 521 | #Cell("DQSDLLC"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 541 | #Cell("AND2"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 561 | #Cell("FD1P3JX"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 581 | #Cell("FL1S1AY"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 601 | #Cell("LB2P3AY"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 621 | #Cell("MUX321"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 641 | #Cell("OR2"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 661 | #Cell("XNOR3"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 681 | Cell("CLKDIVC"), | COMMENT |
| LOW | techlibs/lattice/cells_xtra.py | 701 | #Cell("DLLDELC"), | COMMENT |
| LOW | techlibs/common/gen_fine_ffs.py | 1 | TEMPLATES = [ | COMMENT |
| LOW | techlibs/common/gen_fine_ffs.py | 41 | Q <= D; | COMMENT |
| LOW | techlibs/common/gen_fine_ffs.py | 61 | output reg Q; | COMMENT |
| LOW | techlibs/common/gen_fine_ffs.py | 81 | input D, C, E; | COMMENT |
| LOW | techlibs/common/gen_fine_ffs.py | 141 | //- | COMMENT |
| LOW | techlibs/common/gen_fine_ffs.py | 161 | end | COMMENT |
| LOW | techlibs/common/gen_fine_ffs.py | 221 | //- | COMMENT |
| LOW | techlibs/common/gen_fine_ffs.py | 241 | else if (S == {S:0|1}) | COMMENT |
| LOW | techlibs/common/gen_fine_ffs.py | 301 | //- | COMMENT |
| LOW | techlibs/common/gen_fine_ffs.py | 321 | else | COMMENT |
| LOW | techlibs/common/gen_fine_ffs.py | 341 | input E, D; | COMMENT |
| LOW | techlibs/microchip/LSRAM.txt | 1 | # ISC License | COMMENT |
| LOW | techlibs/microchip/LSRAM.txt | 21 | ram block $__LSRAM_TDP_ { | COMMENT |
| LOW | techlibs/microchip/uSRAM.txt | 1 | # ISC License | COMMENT |
| LOW | techlibs/gatemate/make_lut_tree_lib.py | 101 | def NOT(arg): return FNode("NOT", arg) | COMMENT |
| LOW | techlibs/gatemate/make_lut_tree_lib.py | 141 | # ["$__CC3_AAA", AND(AND(A,B),AND(A,C))], | COMMENT |
| LOW | frontends/verilog/verilog_lexer.h | 1 | #ifndef VERILOG_LEXER_H | COMMENT |
| LOW | backends/smt2/smtbmc.py | 1 | #!@PYTHON_SHEBANG@ | COMMENT |
| LOW | backends/smt2/witness.py | 1 | #!@PYTHON_SHEBANG@ | COMMENT |
| LOW | backends/smt2/smtio.py | 1 | # | COMMENT |
| 99 more matches not shown… | ||||
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| HIGH | backends/smt2/smtbmc_incremental.py | 177 | smt_out.push({"and": "true", "or": "false"}[expr[0]]) | CODE |
| HIGH | passes/pmgen/pmgen.py | 434 | print(" if (cell != nullptr && blacklist_cells.insert(cell).second) {", file=f) | CODE |
| HIGH | passes/pmgen/pmgen.py | 438 | print(" if (rollback == 0 || rollback > rb)", file=f) | CODE |
| HIGH | passes/pmgen/pmgen.py | 786 | print(" if (generate_mode && rng(100) < (found_any_match ? {} : {})) {{".format(block["genargs"][1], | CODE |
| HIGH | tests/gen_tests_makefile.py | 55 | cmd = f"bash -v {sh_file} >{sh_file}.err 2>&1 && mv {sh_file}.err {sh_file}.log" | CODE |
| HIGH | tests/memlib/generate_mk.py | 443 | if (we && ra == wa) | CODE |
| HIGH | tests/memlib/generate_mk.py | 937 | if (we && be[i]) | CODE |
| HIGH | tests/memlib/generate_mk.py | 1439 | ("grden", "rden && rst", "old", False, 1), # selects _clken, simulates _rden | STRING |
| HIGH | tests/memlib/generate_mk.py | 1440 | ("grden_ce", "rden && rst", "old", True, 4), # both of the above | STRING |
| HIGH | tests/memlib/generate_mk.py | 1484 | ("rdenrst_wr_byte", "rden && rst", ["USE_SRST"], "old", 3), | CODE |
| HIGH | tests/memfile/generate_mk.py | 9 | setup = "mkdir -p temp && cp content1.dat temp/content2.dat" | CODE |
| HIGH | tests/fsm/generate_mk.py | 54 | print(' assign rst = rst1 || rst2;') | CODE |
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| LOW | techlibs/fix_mod.py | 6 | CODE | |
| LOW | techlibs/xilinx/cells_xtra.py | 607 | CODE | |
| LOW | …hlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py | 3 | CODE | |
| LOW | techlibs/lattice/cells_xtra.py | 719 | CODE | |
| LOW | techlibs/lattice/cells_xtra_nexus.py | 175 | CODE | |
| LOW | techlibs/gowin/cells_xtra.py | 38 | CODE | |
| LOW | backends/edif/runtest.py | 11 | CODE | |
| LOW | backends/smt2/smtbmc.py | 730 | CODE | |
| LOW | backends/smt2/smtbmc.py | 829 | CODE | |
| LOW | backends/smt2/smtbmc.py | 973 | CODE | |
| LOW | backends/smt2/smtbmc.py | 1082 | CODE | |
| LOW | backends/smt2/smtbmc.py | 1166 | CODE | |
| LOW | backends/smt2/smtbmc.py | 1316 | CODE | |
| LOW | backends/smt2/smtbmc.py | 1386 | CODE | |
| LOW | backends/smt2/smtbmc.py | 1684 | CODE | |
| LOW | backends/smt2/smtbmc.py | 1715 | CODE | |
| LOW | backends/smt2/smtbmc_incremental.py | 374 | CODE | |
| LOW | backends/smt2/witness.py | 187 | CODE | |
| LOW | backends/smt2/witness.py | 365 | CODE | |
| LOW | backends/smt2/witness.py | 337 | CODE | |
| LOW | backends/smt2/smtio.py | 345 | CODE | |
| LOW | backends/smt2/smtio.py | 458 | CODE | |
| LOW | backends/smt2/smtio.py | 557 | CODE | |
| LOW | backends/smt2/smtio.py | 819 | CODE | |
| LOW | backends/smt2/smtio.py | 1195 | CODE | |
| LOW | backends/smt2/smtio.py | 1311 | CODE | |
| LOW | passes/pmgen/pmgen.py | 50 | CODE | |
| LOW | passes/pmgen/pmgen.py | 110 | CODE | |
| LOW | tests/tools/txt2tikztiming.py | 33 | CODE | |
| LOW | tests/bram/generate_mk.py | 14 | CODE | |
| LOW | tests/xprop/test.py | 59 | CODE | |
| LOW | tests/arch/generate_mk.py | 16 | CODE | |
| LOW | tests/arch/gatemate/gen_luttrees.py | 3 | CODE | |
| LOW | tests/rpc/frontend.py | 66 | CODE | |
| LOW | tests/functional/rkt_vcd.py | 13 | CODE | |
| LOW | tests/functional/rkt_vcd.py | 47 | CODE | |
| LOW | tests/functional/smtio.py | 321 | CODE | |
| LOW | tests/functional/smtio.py | 434 | CODE | |
| LOW | tests/functional/smtio.py | 533 | CODE | |
| LOW | tests/functional/smtio.py | 795 | CODE | |
| LOW | tests/functional/smtio.py | 1163 | CODE | |
| LOW | tests/functional/smtio.py | 1269 | CODE | |
| LOW | tests/functional/smt_vcd.py | 42 | CODE | |
| LOW | tests/functional/smt_vcd.py | 15 | CODE | |
| LOW | tests/functional/smt_vcd.py | 47 | CODE | |
| LOW | tests/functional/smt_vcd.py | 143 | CODE | |
| LOW | tests/functional/rtlil_cells.py | 369 | CODE | |
| LOW | docs/util/custom_directives.py | 68 | CODE | |
| LOW | docs/util/cmd_documenter.py | 351 | CODE | |
| LOW | docs/util/cmd_documenter.py | 365 | CODE | |
| LOW | pyosys/generator.py | 295 | CODE | |
| LOW | pyosys/generator.py | 327 | CODE | |
| LOW | pyosys/generator.py | 510 | CODE | |
| LOW | pyosys/generator.py | 647 | CODE |
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| MEDIUM⚡ | tests/simple/generate_mk.py | 8 | # ---------------------- | COMMENT |
| MEDIUM⚡ | tests/simple/generate_mk.py | 10 | # ---------------------- | COMMENT |
| MEDIUM | tests/arch/analogdevices/mem_gen.py | 6 | blockram_template = """# ====================================== | CODE |
| MEDIUM | tests/arch/quicklogic/qlf_k6n10f/mem_gen.py | 6 | blockram_template = """# ====================================== | CODE |
| MEDIUM | tests/rpc/frontend.py | 30 | # ---------------------------------------------------------------------------- | STRING |
| MEDIUM⚡ | tests/simple_abc9/generate_mk.py | 10 | # ---------------------- | COMMENT |
| MEDIUM⚡ | tests/simple_abc9/generate_mk.py | 12 | # ---------------------- | COMMENT |
| MEDIUM⚡ | tests/simple_abc9/generate_mk.py | 18 | # ---------------------- | COMMENT |
| MEDIUM⚡ | tests/simple_abc9/generate_mk.py | 20 | # ---------------------- | COMMENT |
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| LOW | techlibs/gowin/cells_xtra.py | 8 | CODE | |
| LOW | techlibs/gowin/cells_xtra.py | 9 | CODE | |
| LOW | backends/smt2/smtbmc.py | 20 | CODE | |
| LOW | backends/smt2/smtio.py | 24 | CODE | |
| LOW | tests/tools/txt2tikztiming.py | 5 | CODE | |
| LOW | tests/svinterfaces/generate_mk.py | 3 | CODE | |
| LOW | tests/arch/analogdevices/generate_mk.py | 7 | CODE | |
| LOW | tests/arch/analogdevices/mem_gen.py | 1 | CODE | |
| LOW | tests/arch/quicklogic/qlf_k6n10f/generate_mk.py | 7 | CODE | |
| LOW | tests/arch/quicklogic/qlf_k6n10f/mem_gen.py | 1 | CODE | |
| LOW | tests/functional/rkt_vcd.py | 1 | CODE | |
| LOW | tests/functional/smtio.py | 24 | CODE | |
| LOW | tests/functional/smt_vcd.py | 1 | CODE | |
| LOW | tests/functional/smt_vcd.py | 2 | CODE | |
| LOW | tests/functional/smt_vcd.py | 3 | CODE | |
| LOW | tests/functional/rtlil_cells.py | 2 | CODE | |
| LOW | docs/util/cell_documenter.py | 2 | CODE | |
| LOW | docs/util/custom_directives.py | 3 | CODE | |
| LOW | docs/util/cmd_documenter.py | 2 | CODE | |
| LOW | docs/util/cmd_documenter.py | 4 | CODE | |
| LOW | examples/python-api/script.py | 6 | CODE | |
| LOW | kernel/cellhelp.py | 3 | CODE |
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| MEDIUM | libs/minisat/Vec.h | 81 | // happen given the way capacities are calculated (below). Essentially, all capacities are | COMMENT |
| MEDIUM | pyosys/hashlib.h | 281 | // repr(set(s)) where s is iterable would be more terse/robust | COMMENT |
| MEDIUM | pyosys/hashlib.h | 408 | // repr(dict(s)) where s is iterable would be more terse/robust | COMMENT |
| MEDIUM | pyosys/hashlib.h | 512 | // repr(dict(s)) where s is iterable would be more terse/robust | COMMENT |
| MEDIUM | kernel/drivertools.h | 1118 | // Essentially a dict<DriveBitId, pool<DriveBitId>> but using less memory | COMMENT |
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| LOW | backends/smt2/smtbmc_incremental.py | 612 | except Exception as e: | CODE |
| MEDIUM⚡ | tests/simple/generate_mk.py | 12 | print("Error: Icarus Verilog 'iverilog' not found.", file=sys.stderr) | CODE |
| LOW | tests/memories/validate.py | 86 | except Exception as e: | CODE |
| LOW | tests/memories/validate.py | 92 | except Exception as e: | CODE |
| MEDIUM⚡ | tests/simple_abc9/generate_mk.py | 14 | print("Error: Icarus Verilog 'iverilog' not found.", file=sys.stderr) | CODE |
| LOW | docs/util/cell_documenter.py | 221 | except Exception as exc: | STRING |
| LOW | docs/util/cmd_documenter.py | 263 | except Exception as exc: | STRING |
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| LOW | backends/smt2/smtbmc.py | 1490 | def print_failed_asserts_worker(mod, state, path, extrainfo, infomap, infokey=()): | STRING |
| LOW | backends/smt2/smtbmc.py | 1628 | def smt_assert_design_assumes(step): | STRING |
| LOW | backends/smt2/smtbmc.py | 1802 | def report_tracked_assumptions(msg): | STRING |
| LOW | backends/smt2/smtbmc_incremental.py | 427 | def cmd_assert_design_assumes(self, cmd): | CODE |
| LOW | backends/smt2/smtbmc_incremental.py | 447 | def cmd_get_unsat_assumptions(self, cmd): | CODE |
| LOW | backends/smt2/smtio.py | 985 | def get_raw_unsat_assumptions(self): | CODE |
| LOW | tests/functional/test_smtbmc_witness_mismatch.py | 76 | def assert_no_mismatch_message(result): | CODE |
| LOW | tests/functional/test_smtbmc_witness_mismatch.py | 82 | def assert_has_mismatch_message(result, msg): | CODE |
| LOW | tests/functional/test_smtbmc_witness_mismatch.py | 143 | def test_allowed_extra_signal_in_design(tmp_path): | STRING |
| LOW | tests/functional/test_smtbmc_witness_mismatch.py | 169 | def test_allowed_extra_memory_in_design(tmp_path): | STRING |
| LOW | tests/functional/smtio.py | 961 | def get_raw_unsat_assumptions(self): | CODE |
| LOW | pyosys/generator.py | 378 | def make_preprocessor_options(self, build_dir): | CODE |
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| LOW | tests/vloghtb/common.sh | 13 | # Usage: | COMMENT |
| LOW | tests/vloghtb/common.sh | 40 | # Usage: | COMMENT |
| LOW | tests/vloghtb/common.sh | 74 | # Usage: | COMMENT |
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| LOW⚡ | tests/simple/generate_mk.py | 9 | # Check if iverilog is installed | COMMENT |
| LOW⚡ | tests/simple_abc9/generate_mk.py | 11 | # Check if iverilog is installed | COMMENT |
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| LOW | docs/util/cell_documenter.py | 15 | logger = logging.getLogger(__name__) | CODE |
| LOW | docs/util/RtlilLexer.py | 4 | __all__ = ['RtlilLexer'] | CODE |
| LOW | docs/util/cmd_documenter.py | 15 | logger = logging.getLogger(__name__) | CODE |
| LOW | pyosys/modinit.py | 19 | __all__ = ["libyosys"] | CODE |
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| MEDIUM | tests/functional/smt_vcd.py | 136 | # Create a single assertion covering all timesteps | COMMENT |
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| LOW | .github/workflows/test-compile.yml | 50 | # newest, make sure to update maximum standard step to match | COMMENT |
| LOW | .github/actions/setup-build-env/action.yml | 32 | # if updating common/build/docs dependencies, make sure to update README.md | COMMENT |
| Severity | File | Line | Snippet | Context |
|---|---|---|---|---|
| LOW | docs/util/cmd_documenter.py | 61 | CODE |