Repository Analysis

NawfalMotii79/PLFM_RADAR

Open-source, low-cost 10.5 GHz PLFM phased array RADAR system

27.5 Moderate AI signal View on GitHub

Analysis Overview

This report presents the forensic synthetic code analysis of NawfalMotii79/PLFM_RADAR, a PLSQL project with 23,185 GitHub stars. SynthScan v2.0 examined 75,937 lines of code across 270 source files, recording 1004 pattern matches distributed across 17 syntactic categories. The overall adjusted score of 27.5 places this repository in the Moderate AI signal band.

The scanner applied 160+ deterministic lexical heuristics, multi-line block detectors, abstract syntax tree depth profilers, and a cross-file Jaccard similarity matrix to construct a statistically normalised synthetic code estimate. All matches are individually weighted by severity coefficient and contextual multiplier before summation, and the resulting headline score is temporally discounted to account for the repository's development history relative to the commercial emergence of large language model coding tooling (November 2022 onward).

27.5
Adjusted Score
27.5
Raw Score
100%
Time Factor
2026-06-17
Last Push
23.2K
Stars
PLSQL
Language
75.9K
Lines of Code
270
Files
1.0K
Pattern Hits
2026-08-02
Scan Date
0.06
HC Hit Rate

What These Metrics Mean

Adjusted Score
Primary synthetic code indicator. Raw score normalised per 1,000 lines of code and multiplied by the temporal discount factor. This is the definitive comparative metric — use it to rank repositories by AI authorship density.
Raw Score
The unmodified sum of all severity-weighted, context-multiplied pattern match scores before temporal discounting. Reflects the absolute signal strength independent of when the repository was last active.
Time Factor
The temporal discount multiplier (0–100%) applied to the raw score. Repositories last updated before ChatGPT's launch (Nov 2022) receive a 5% factor. Full signal is only assigned to repositories active in the post-adoption era (Jan 2024+).
Pattern Hits
Total count of individual pattern matches across all files and categories. A high hit count with a low score may indicate a very large codebase with isolated AI snippets; a low count with a high score indicates dense, concentrated AI signatures.
HC Hit Rate
High+Critical pattern hits per file, averaged across the repository. This orthogonal signal catches repositories where a few files are densely packed with high-severity AI tells — a strong indicator even when the normalised score appears moderate due to codebase size.
Lines of Code / Files
Total lines and files analysed. The scanner examines 94 file extensions. These denominators are used to normalise the score, enabling fair comparison between repositories of vastly different sizes.

Score History

This chart maps the temporal evolution of the adjusted synthetic code score across successive scan runs. An upward trajectory indicates ongoing incorporation of AI-generated code or expanding LLM-assisted scaffolding; a stable or declining trajectory may reflect active human refactoring, code removal, or the adoption of stricter authorship policies. The dashed secondary line (right axis) independently tracks total raw pattern hit count, which can diverge from the normalised score when codebase size changes significantly between scans.

Severity Breakdown

Classifies detected patterns by their diagnostic confidence and structural impact. CRITICAL patterns (coefficient 10) represent definitive synthetic signatures — hallucinated imports, explicit LLM attribution metadata — virtually never produced by human authors. HIGH (5) indicates strong structural tells such as cross-file repetition or cross-linguistic idioms. MEDIUM (2) covers recognisable conversational padding and AI-specific vocabulary. LOW (1) captures subtle indicators like tautological comments and generic boilerplate that require density to carry independent signal.

CRITICAL 0HIGH 15MEDIUM 502LOW 487

Directory Score Breakdown

This horizontal bar chart decomposes the repository's raw synthetic code score by top-level directory, allowing you to pinpoint precisely which modules or components carry the highest AI authorship density. Directories with disproportionately high scores relative to their size warrant targeted manual review: concentrated AI signatures often trace back to mass-generated configuration layers, auto-ported test suites, LLM-scaffolded boilerplate classes, or entire subsystems authored under heavy copilot assistance. Use this view to prioritise your human code-review effort.

Pattern Findings

The scanner identified 1004 distinct pattern matches across 17 syntactic categories. Each entry below represents a discrete location in the source code where the engine recorded a statistically significant AI authorship indicator. Expand any category row to inspect the individual file paths, line numbers, code snippets, and the lexical context (CODE, COMMENT, or STRING) in which each match was detected.

Reading the findings table: The Severity column indicates the diagnostic confidence level (CRITICAL / HIGH / MEDIUM / LOW). The Context column identifies whether the match occurred inside executable code, an inline comment, or a string literal — comment-context matches receive a ×1.5 weight because LLMs systematically over-annotate. The ⚡ bolt icon marks clustered matches: three or more patterns within a 10-line window, each receiving an additional ×1.5 density multiplier as dense clusters constitute far stronger evidence of synthetic authorship than isolated hits.

Decorative Section Separators493 hits · 1486 pts
SeverityFileLineSnippetContext
MEDIUMpyproject.toml19# ---------------------------------------------------------------------------COMMENT
MEDIUMpyproject.toml21# ---------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tools/uart_capture.py44# ---------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tools/uart_capture.py46# ---------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tools/uart_capture.py89# ---------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tools/uart_capture.py91# ---------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tools/uart_capture.py175# ---------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tools/uart_capture.py177# ---------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tools/uart_capture.py223# ---------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tools/uart_capture.py225# ---------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tools/uart_capture.py312# ---------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tools/uart_capture.py314# ---------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tests/cross_layer/contract_parser.py23# ---------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tests/cross_layer/contract_parser.py25# ---------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tests/cross_layer/contract_parser.py35# ===================================================================COMMENT
MEDIUM9_Firmware/tests/cross_layer/contract_parser.py37# ===================================================================COMMENT
MEDIUM9_Firmware/tests/cross_layer/contract_parser.py105# ===================================================================COMMENT
MEDIUM9_Firmware/tests/cross_layer/contract_parser.py107# ===================================================================COMMENT
MEDIUM9_Firmware/tests/cross_layer/contract_parser.py276# ===================================================================COMMENT
MEDIUM9_Firmware/tests/cross_layer/contract_parser.py278# ===================================================================COMMENT
MEDIUM9_Firmware/tests/cross_layer/contract_parser.py667# ===================================================================COMMENT
MEDIUM9_Firmware/tests/cross_layer/contract_parser.py669# ===================================================================COMMENT
MEDIUM9_Firmware/tests/cross_layer/contract_parser.py753# ===================================================================COMMENT
MEDIUM9_Firmware/tests/cross_layer/contract_parser.py755# ===================================================================COMMENT
MEDIUM…irmware/tests/cross_layer/test_cross_layer_contract.py233# ===================================================================COMMENT
MEDIUM…irmware/tests/cross_layer/test_cross_layer_contract.py235# ===================================================================COMMENT
MEDIUM…irmware/tests/cross_layer/test_cross_layer_contract.py50# ===================================================================COMMENT
MEDIUM…irmware/tests/cross_layer/test_cross_layer_contract.py52# ===================================================================COMMENT
MEDIUM…irmware/tests/cross_layer/test_cross_layer_contract.py164# ===================================================================COMMENT
MEDIUM…irmware/tests/cross_layer/test_cross_layer_contract.py166# ===================================================================COMMENT
MEDIUM…irmware/tests/cross_layer/test_cross_layer_contract.py741# ===================================================================COMMENT
MEDIUM…irmware/tests/cross_layer/test_cross_layer_contract.py743# ===================================================================COMMENT
MEDIUM…irmware/tests/cross_layer/test_cross_layer_contract.py939# ===================================================================COMMENT
MEDIUM…irmware/tests/cross_layer/test_cross_layer_contract.py941# ===================================================================COMMENT
MEDIUM…irmware/tests/cross_layer/test_cross_layer_contract.py1122# ===================================================================COMMENT
MEDIUM…irmware/tests/cross_layer/test_cross_layer_contract.py1124# ===================================================================COMMENT
MEDIUM9_Firmware/tests/cross_layer/adar1000_vm_reference.py37# ----------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tests/cross_layer/adar1000_vm_reference.py40# ----------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tests/cross_layer/adar1000_vm_reference.py93# ----------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tests/cross_layer/adar1000_vm_reference.py98# ----------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tests/cross_layer/adar1000_vm_reference.py181# ----------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/tests/cross_layer/adar1000_vm_reference.py183# ----------------------------------------------------------------------------COMMENT
MEDIUM9_Firmware/9_3_GUI/requirements_pyqt_gui.txt2# ======================================================COMMENT
MEDIUM9_Firmware/9_3_GUI/test_GUI_V65_Tk.py31 # ----------------------------------------------------------------COMMENT
MEDIUM9_Firmware/9_3_GUI/test_GUI_V65_Tk.py33 # ----------------------------------------------------------------COMMENT
MEDIUM9_Firmware/9_3_GUI/test_GUI_V65_Tk.py71 # ----------------------------------------------------------------COMMENT
MEDIUM9_Firmware/9_3_GUI/test_GUI_V65_Tk.py73 # ----------------------------------------------------------------COMMENT
MEDIUM9_Firmware/9_3_GUI/test_GUI_V65_Tk.py121 # ----------------------------------------------------------------COMMENT
MEDIUM9_Firmware/9_3_GUI/test_GUI_V65_Tk.py123 # ----------------------------------------------------------------COMMENT
MEDIUM9_Firmware/9_3_GUI/test_GUI_V65_Tk.py244 # ----------------------------------------------------------------COMMENT
MEDIUM9_Firmware/9_3_GUI/test_GUI_V65_Tk.py246 # ----------------------------------------------------------------COMMENT
MEDIUM9_Firmware/9_3_GUI/test_GUI_V65_Tk.py778# =====================================================================COMMENT
MEDIUM9_Firmware/9_3_GUI/test_GUI_V65_Tk.py780# =====================================================================COMMENT
MEDIUM9_Firmware/9_3_GUI/test_GUI_V65_Tk.py672# =============================================================================COMMENT
MEDIUM9_Firmware/9_3_GUI/test_GUI_V65_Tk.py674# =============================================================================COMMENT
MEDIUM9_Firmware/9_3_GUI/GUI_V6_Demo.py3# =============================================================================COMMENT
MEDIUM9_Firmware/9_3_GUI/GUI_V6_Demo.py7# =============================================================================COMMENT
MEDIUM9_Firmware/9_3_GUI/GUI_V6_Demo.py32# ============================================================================COMMENT
MEDIUM9_Firmware/9_3_GUI/GUI_V6_Demo.py34# ============================================================================COMMENT
MEDIUM9_Firmware/9_3_GUI/GUI_V6_Demo.py58# ============================================================================COMMENT
433 more matches not shown…
Over-Commented Block111 hits · 104 pts
SeverityFileLineSnippetContext
LOW9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.h61/* Private defines -----------------------------------------------------------*/COMMENT
LOW9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.h81#define ADAR_2_CS_3V3_GPIO_Port GPIOACOMMENT
LOW9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.h101#define EN_P_1V8_FPGA_GPIO_Port GPIOECOMMENT
LOW9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.h121#define EN_P_1V8_CLOCK_GPIO_Port GPIOGCOMMENT
LOW9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.h141#define EN_DIS_RFPA_VDD_GPIO_Port GPIODCOMMENT
LOW9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.h161#define ADF4382_TX_DELADJ_Pin GPIO_PIN_13COMMENT
LOW…mware/9_1_Microcontroller/9_1_3_C_Cpp_Code/um982_gps.h21#include <math.h>COMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp21#include "usb_device.h"COMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp41#include <stdio.h>COMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp901 // Blink LED pattern based on error codeCOMMENT
LOW9_Firmware/9_1_Microcontroller/tests/stm32_hal_mock.h21#include <string.h>COMMENT
LOW9_Firmware/9_1_Microcontroller/tests/stm32_hal_mock.h61#define GPIO_PIN_8 ((uint16_t)0x0100)COMMENT
LOW…_1_Microcontroller/tests/test_bug7_gpio_pin_conflict.c21COMMENT
LOW…ware/9_1_Microcontroller/tests/test_agc_outer_loop.cpp1// test_agc_outer_loop.cpp -- C++ unit tests for ADAR1000_AGC outer-loop AGCCOMMENT
LOW…rmware/9_1_Microcontroller/tests/shims/stm32f7xx_hal.h1/* shim: redirect stm32f7xx_hal.h -> our mock */COMMENT
LOW9_Firmware/9_1_Microcontroller/tests/shims/main.h1/* shim: redirect main.h -> our mock + pin defines from real main.h */COMMENT
LOW9_Firmware/9_1_Microcontroller/tests/shims/main.h21#define AD9523_RESET_Pin GPIO_PIN_6COMMENT
LOW9_Firmware/9_1_Microcontroller/tests/shims/main.h41#define LED_1_Pin GPIO_PIN_12COMMENT
LOW9_Firmware/9_1_Microcontroller/tests/shims/main.h61#define EN_P_3V3_CLOCK_GPIO_Port GPIOGCOMMENT
LOW9_Firmware/9_1_Microcontroller/tests/shims/main.h81#define ADF4382_TX_CE_Pin GPIO_PIN_15COMMENT
LOW9_Firmware/9_1_Microcontroller/tests/shims/main.h101#define EN_P_3V3_VDD_SW_Pin GPIO_PIN_15COMMENT
LOW9_Firmware/9_1_Microcontroller/tests/shims/main.h121#define DAC_2_VG_LDAC_Pin GPIO_PIN_9COMMENT
LOW9_Firmware/9_1_Microcontroller/tests/shims/diag_log.h1/* shim: diag_log.h -- disable DIAG macros for test builds */COMMENT
LOW9_Firmware/9_1_Microcontroller/tests/shims/no_os_spi.h1/* shim: redirect no_os_spi.h -> our mock types */COMMENT
LOW9_Firmware/9_1_Microcontroller/tests/shims/adf4382.h1/* shim: redirect adf4382.h -> our mock types */COMMENT
LOW…Firmware/9_1_Microcontroller/tests/shims/no_os_units.h1/* shim: redirect no_os_units.h -> minimal defines */COMMENT
LOW…are/9_1_Microcontroller/tests/shims/adf4382a_manager.h21/* RX pins: GPIOG pins 6-10 */COMMENT
LOW…are/9_1_Microcontroller/tests/shims/adf4382a_manager.h41#define TX_CS_GPIO_Port GPIOGCOMMENT
LOW…are/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ad9523.h41/* Registers */COMMENT
LOW…are/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ad9523.h61#define AD9523_PLL1_REF_B_DIVIDER (AD9523_R2B | 0x13)COMMENT
LOW…are/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ad9523.h81#define AD9523_PLL1_OUTPUT_CHANNEL_CTRL (AD9523_R1B | 0x1BB)COMMENT
LOW…are/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ad9523.h101#define AD9523_READBACK_CTRL_READ_BUFFERED (1 << 0)COMMENT
LOW…are/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ad9523.h121#define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN (1 << 2)COMMENT
LOW…are/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ad9523.h141#define AD9523_PLL1_BYPASS_REFA_DIV (1 << 0)COMMENT
LOW…are/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ad9523.h161#define AD9523_PLL2_BACKLASH_PW_HIGH (2 << 2)COMMENT
LOW…are/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ad9523.h181#define AD9523_PLL2_LOOP_FILTER_RZERO(x) (((x) & 0x7) << 3)COMMENT
LOW…are/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ad9523.h201#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2 (1 << 6)COMMENT
LOW…are/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ad9523.h221#define AD9523_READBACK_0_STAT_PLL2_REF_CLK (1 << 7)COMMENT
LOW…1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_AGC.h1// ADAR1000_AGC.h -- STM32 outer-loop AGC for ADAR1000 RX VGA gainCOMMENT
LOW…1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_AGC.h21#define ADAR1000_AGC_HCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp21};COMMENT
LOW…9_1_Microcontroller/9_1_1_C_Cpp_Libraries/no_os_mdio.h41#define NO_OS_MDIO_C45_START 0COMMENT
LOW…crocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.h181#define REG_SCRATCHPAD 0x00ACOMMENT
LOW…crocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.h201#define REG_CH2_TX_PHS_Q 0x023COMMENT
LOW…crocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.h221#define REG_PA_CH1_BIAS_OFF 0x046COMMENT
LOW…/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/no_os_i3c.h41#define _NO_OS_I3C_H_COMMENT
LOW…/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/no_os_i3c.h61#define NO_OS_I3C_CCC_BCAST 0COMMENT
LOW…/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/no_os_i3c.h81#define NO_OS_I3C_CCC_DISEC_BCAST 0x01 | NO_OS_I3C_CCC_SET_DEFCOMMENT
LOW…/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/no_os_i3c.h101#define NO_OS_I3C_CCC_SETDASA NO_OS_I3C_CCC_ID(0x7, NO_OS_I3C_CCC_DIRECT)COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/stm32f7xx_hal_conf.h81/* #define HAL_EXTI_MODULE_ENABLED */COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/stm32f7xx_hal_conf.h141COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/stm32f7xx_hal_conf.h161#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/stm32f7xx_hal_conf.h181#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/stm32f7xx_hal_conf.h221/* DP83848_PHY_ADDRESS Address*/COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/stm32f7xx_hal_conf.h241#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/stm32f7xx_hal_conf.h281#endif /* HAL_GPIO_MODULE_ENABLED */COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/stm32f7xx_hal_conf.h301#endif /* HAL_CEC_MODULE_ENABLED */COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/stm32f7xx_hal_conf.h321#endif /* HAL_DCMI_MODULE_ENABLED */COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/stm32f7xx_hal_conf.h341#endif /* HAL_NOR_MODULE_ENABLED */COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/stm32f7xx_hal_conf.h361#endif /* HAL_I2S_MODULE_ENABLED */COMMENT
51 more matches not shown…
Hyper-Verbose Identifiers130 hits · 98 pts
SeverityFileLineSnippetContext
LOW9_Firmware/tests/cross_layer/contract_parser.py130def parse_python_packet_constants(filepath: Path | None = None) -> dict[str, PacketConstants]:CODE
LOW9_Firmware/tests/cross_layer/contract_parser.py155def parse_python_data_packet_fields(filepath: Path | None = None) -> list[DataPacketField]:CODE
LOW9_Firmware/tests/cross_layer/contract_parser.py221def parse_python_status_fields(filepath: Path | None = None) -> list[StatusWordField]:CODE
LOW9_Firmware/tests/cross_layer/contract_parser.py375def parse_verilog_reset_defaults(filepath: Path | None = None) -> dict[str, int]:CODE
LOW9_Firmware/tests/cross_layer/contract_parser.py412def parse_verilog_register_widths(filepath: Path | None = None) -> dict[str, int]:CODE
LOW9_Firmware/tests/cross_layer/contract_parser.py435def parse_verilog_packet_constants(CODE
LOW9_Firmware/tests/cross_layer/contract_parser.py528def parse_verilog_status_word_concats(CODE
LOW9_Firmware/tests/cross_layer/contract_parser.py558def get_usb_interface_port_widths(filepath: Path | None = None) -> dict[str, int]:CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py240 def test_python_opcodes_match_ground_truth(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py249 def test_ground_truth_opcodes_in_python(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py257 def test_verilog_opcodes_match_ground_truth(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py265 def test_ground_truth_opcodes_in_verilog(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py273 def test_python_verilog_bidirectional_match(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py282 def test_verilog_register_names_match(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py813 def test_ground_truth_quadrant_symmetry(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py823 def test_ground_truth_cardinal_points(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py833 def test_firmware_vm_i_matches_datasheet(self, cpp_source):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py81def _strip_cxx_comments_and_strings(src: str) -> str:CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py297 def test_verilog_register_widths(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py309 def test_verilog_opcode_bit_slices(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py370 def test_python_status_mode_position(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py394 def test_python_packet_constants(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py408 def test_verilog_packet_constants(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py422 def test_python_verilog_constants_agree(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py435 def test_verilog_reset_defaults(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py468 def test_fpga_agc_enable_boot_default_off(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py479 def test_mcu_agc_constructor_default_off(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py503 def test_boot_invariant_all_layers_agc_off(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py631 def test_verilog_data_mux_field_positions(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py650 def test_python_data_packet_byte_positions(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py673 def test_field_order_and_sizes(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py779 def test_ground_truth_table_shape(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py792 def test_ground_truth_byte_format(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py855 def test_firmware_vm_q_matches_datasheet(self, cpp_source):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py876 def test_vm_gain_table_is_not_reintroduced(self, cpp_source):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py900 def test_adversarial_corruption_is_detected(self):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py1004 def test_data_packet_python_round_trip(self, tb_results):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py1047 def test_status_packet_python_round_trip(self, tb_results):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py1184 def test_default_values_round_trip(self, stub_binary):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py1214 def test_distinctive_values_round_trip(self, stub_binary):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py1244 def test_truncated_packet_rejected(self, stub_binary):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py1252 def test_bad_markers_rejected(self, stub_binary):CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py1273 def test_python_c_packet_format_agreement(self, stub_binary):CODE
LOW9_Firmware/9_3_GUI/GUI_V5_Demo.py257 def _parse_binary_gps_with_pitch(self, data):CODE
LOW9_Firmware/9_3_GUI/GUI_V5_Demo.py663 def generate_map_html_content(self, gps_data, targets, coverage_radius):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py34 def test_build_command_trigger(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py43 def test_build_command_cfar_alpha(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py50 def test_build_command_status_request(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py57 def test_build_command_with_addr(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py65 def test_build_command_value_clamp(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py87 def test_parse_data_packet_basic(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py97 def test_parse_data_packet_with_detection(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py103 def test_parse_data_packet_negative_values(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py113 def test_parse_data_packet_too_short(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py116 def test_parse_data_packet_wrong_header(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py180 def test_parse_status_range_mode(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py185 def test_parse_status_too_short(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py188 def test_parse_status_wrong_header(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py193 def test_parse_status_wrong_footer(self):CODE
LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py198 def test_parse_status_self_test_all_pass(self):CODE
70 more matches not shown…
Structural Annotation Overuse42 hits · 80 pts
SeverityFileLineSnippetContext
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp359 // Step 1: Initialize ADTR1107 power sequenceCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp369 // Step 2: Initialize all ADAR1000 devicesCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp379 // Step 3: Perform system calibrationCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp389 // Step 4: Set to safe TX modeCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp404 // Step 1: Set all devices to RX mode (safest state)COMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp409 // Step 2: Disable PA power suppliesCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp414 // Step 3: Set PA biases to safe valuesCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp424 // Step 4: Disable LNA power supplyCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp429 // Step 5: Set LNA bias to safe valueCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp436 // Step 6: Disable switch power suppliesCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp454 // Step 1: Connect all GND pins to ground (assumed in hardware)COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp457 // Step 2: Set VDD_SW to 3.3VCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp462 // Step 3: Set VSS_SW to -3.3VCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp467 // Step 4: Set CTRL_SW to RX mode initially via GPIOCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp472 // Step 5: Set VGG_LNA to 0COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp480 // Step 6: Set VDD_LNA to 0V for TX modeCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp485 // Step 7: Set VGG_PA to safe negative voltage (PA off for TX mode)COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp499 // Step 8: Set VDD_PA to 0V (PA powered up for TX mode)COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp504 // Step 9: Adjust VGG_PA voltage between −1.75 V and −0.25 V to achieve the desired IDQ_PA=220mACOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp573 // Step 1: Disable LNA power firstCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp578 // Step 2: Set LNA bias to safe off valueCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp585 // Step 3: Enable PA powerCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp590 // Step 4: Set PA bias to operational valueCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp614 // Step 1: Disable PA power firstCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp619 // Step 2: Set PA bias to safe negative voltageCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp630 // Step 3: Enable LNA powerCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp635 // Step 4: Set LNA bias to operational valueCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp643 // Step 5: Set TR switch to RX modeCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp601 // Step 5: Set TR switch to TX modeCOMMENT
LOW9_Firmware/9_3_GUI/smoke_test.py84 # Step 1: ConnectCOMMENT
LOW9_Firmware/9_3_GUI/smoke_test.py89 # Step 2: Send self-test trigger (opcode 0x30)COMMENT
LOW9_Firmware/9_3_GUI/smoke_test.py96 # Step 3: Wait for completion and read resultsCOMMENT
LOW9_Firmware/9_3_GUI/smoke_test.py104 # Step 4: Decode resultsCOMMENT
LOW9_Firmware/9_3_GUI/smoke_test.py108 # Step 5: ADC data dump (if requested and test 4 passed)COMMENT
LOW9_Firmware/9_3_GUI/smoke_test.py112 # Step 6: SummaryCOMMENT
LOW9_Firmware/9_3_GUI/GUI_V5.py1323 # Step 12: Send start flag to STM32 via USBCOMMENT
LOW9_Firmware/9_3_GUI/GUI_V5.py1328 # Step 13: Send settings to STM32 via USBCOMMENT
LOW9_Firmware/9_2_FPGA/adc_clk_mmcm_integration.md57### Step 1: Modify `ad9484_interface_400m.v`COMMENT
LOW9_Firmware/9_2_FPGA/adc_clk_mmcm_integration.md85### Step 2: Gate reset on MMCM lock (recommended)COMMENT
LOW9_Firmware/9_2_FPGA/adc_clk_mmcm_integration.md113### Step 3: Add constraint fileCOMMENT
LOW9_Firmware/9_2_FPGA/adc_clk_mmcm_integration.md124### Step 4: Add to build scriptCOMMENT
LOW9_Firmware/9_2_FPGA/adc_clk_mmcm_integration.md133### Step 5: VerifyCOMMENT
Verbosity Indicators37 hits · 73 pts
SeverityFileLineSnippetContext
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp359 // Step 1: Initialize ADTR1107 power sequenceCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp369 // Step 2: Initialize all ADAR1000 devicesCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp379 // Step 3: Perform system calibrationCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp389 // Step 4: Set to safe TX modeCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp404 // Step 1: Set all devices to RX mode (safest state)COMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp409 // Step 2: Disable PA power suppliesCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp414 // Step 3: Set PA biases to safe valuesCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp424 // Step 4: Disable LNA power supplyCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp429 // Step 5: Set LNA bias to safe valueCOMMENT
LOW…Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp436 // Step 6: Disable switch power suppliesCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp454 // Step 1: Connect all GND pins to ground (assumed in hardware)COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp457 // Step 2: Set VDD_SW to 3.3VCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp462 // Step 3: Set VSS_SW to -3.3VCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp467 // Step 4: Set CTRL_SW to RX mode initially via GPIOCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp472 // Step 5: Set VGG_LNA to 0COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp480 // Step 6: Set VDD_LNA to 0V for TX modeCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp485 // Step 7: Set VGG_PA to safe negative voltage (PA off for TX mode)COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp499 // Step 8: Set VDD_PA to 0V (PA powered up for TX mode)COMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp504 // Step 9: Adjust VGG_PA voltage between −1.75 V and −0.25 V to achieve the desired IDQ_PA=220mACOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp573 // Step 1: Disable LNA power firstCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp578 // Step 2: Set LNA bias to safe off valueCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp585 // Step 3: Enable PA powerCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp590 // Step 4: Set PA bias to operational valueCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp614 // Step 1: Disable PA power firstCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp619 // Step 2: Set PA bias to safe negative voltageCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp630 // Step 3: Enable LNA powerCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp635 // Step 4: Set LNA bias to operational valueCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp643 // Step 5: Set TR switch to RX modeCOMMENT
LOW…ocontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp601 // Step 5: Set TR switch to TX modeCOMMENT
LOW9_Firmware/9_3_GUI/smoke_test.py84 # Step 1: ConnectCOMMENT
LOW9_Firmware/9_3_GUI/smoke_test.py89 # Step 2: Send self-test trigger (opcode 0x30)COMMENT
LOW9_Firmware/9_3_GUI/smoke_test.py96 # Step 3: Wait for completion and read resultsCOMMENT
LOW9_Firmware/9_3_GUI/smoke_test.py104 # Step 4: Decode resultsCOMMENT
LOW9_Firmware/9_3_GUI/smoke_test.py108 # Step 5: ADC data dump (if requested and test 4 passed)COMMENT
LOW9_Firmware/9_3_GUI/smoke_test.py112 # Step 6: SummaryCOMMENT
LOW9_Firmware/9_3_GUI/GUI_V5.py1323 # Step 12: Send start flag to STM32 via USBCOMMENT
LOW9_Firmware/9_3_GUI/GUI_V5.py1328 # Step 13: Send settings to STM32 via USBCOMMENT
Unused Imports77 hits · 58 pts
SeverityFileLineSnippetContext
LOW9_Firmware/tests/cross_layer/contract_parser.py17CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py27CODE
LOW9_Firmware/tests/cross_layer/adar1000_vm_reference.py33CODE
LOW9_Firmware/9_3_GUI/GUI_V6.py36CODE
LOW9_Firmware/9_3_GUI/GUI_V6.py37CODE
LOW9_Firmware/9_3_GUI/test_v7.py270CODE
LOW9_Firmware/9_3_GUI/v7/models.py20CODE
LOW9_Firmware/9_3_GUI/v7/models.py21CODE
LOW9_Firmware/9_3_GUI/v7/models.py28CODE
LOW9_Firmware/9_3_GUI/v7/models.py29CODE
LOW9_Firmware/9_3_GUI/v7/models.py30CODE
LOW9_Firmware/9_3_GUI/v7/models.py37CODE
LOW9_Firmware/9_3_GUI/v7/models.py44CODE
LOW9_Firmware/9_3_GUI/v7/models.py51CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py11CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py27CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py27CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py27CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py27CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py27CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py27CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py27CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py27CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py27CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py40CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py40CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py40CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py40CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py40CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py50CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py50CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py56CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py56CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py63CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py63CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py63CODE
17 more matches not shown…
Cross-Language Confusion12 hits · 50 pts
SeverityFileLineSnippetContext
HIGH9_Firmware/9_3_GUI/GUI_V5_Demo.py555 if (window.initialTargets && window.initialTargets.length > 0) {CODE
HIGH9_Firmware/9_3_GUI/GUI_V5_Demo.py615 targetMarkers.push(targetMarker);CODE
HIGH9_Firmware/9_3_GUI/GUI_PyQt_Map.py443 var bridge = null;CODE
HIGH9_Firmware/9_3_GUI/GUI_PyQt_Map.py444 var currentTileLayer = null;CODE
HIGH9_Firmware/9_3_GUI/GUI_V6.py195 targetMarkers.forEach(marker => marker.setMap(null));CODE
HIGH9_Firmware/9_3_GUI/GUI_V6.py233 targetMarkers.push(targetMarker);CODE
HIGH9_Firmware/9_3_GUI/GUI_V5.py208 targetMarkers.forEach(marker => marker.setMap(null));CODE
HIGH9_Firmware/9_3_GUI/GUI_V5.py244 targetMarkers.push(targetMarker);CODE
HIGH9_Firmware/9_3_GUI/v7/map_widget.py252var bridge = null;STRING
HIGH9_Firmware/9_3_GUI/v7/map_widget.py253var currentTileLayer = null;STRING
HIGH9_Firmware/9_2_FPGA/tb/cosim/fpga_model.py672 Cycle 1: valid_sync = valid_i_reg && valid_q_regSTRING
HIGH…rmware/9_2_FPGA/tb/cosim/real_data/golden_reference.py799 (bin_within_sf < width || bin_within_sf > (15 - width + 1))STRING
Deep Nesting49 hits · 43 pts
SeverityFileLineSnippetContext
LOW9_Firmware/tools/uart_capture.py227CODE
LOW9_Firmware/tests/cross_layer/contract_parser.py757CODE
LOW…irmware/tests/cross_layer/test_cross_layer_contract.py81CODE
LOW9_Firmware/9_3_GUI/smoke_test.py123CODE
LOW9_Firmware/9_3_GUI/GUI_V5_Demo.py737CODE
LOW9_Firmware/9_3_GUI/GUI_V6_Demo.py172CODE
LOW9_Firmware/9_3_GUI/GUI_V6_Demo.py977CODE
LOW9_Firmware/9_3_GUI/radar_protocol.py265CODE
LOW9_Firmware/9_3_GUI/radar_protocol.py734CODE
LOW9_Firmware/9_3_GUI/GUI_V6.py268CODE
LOW9_Firmware/9_3_GUI/GUI_V6.py415CODE
LOW9_Firmware/9_3_GUI/GUI_V6.py535CODE
LOW9_Firmware/9_3_GUI/GUI_V6.py1321CODE
LOW9_Firmware/9_3_GUI/GUI_V6.py1393CODE
LOW9_Firmware/9_3_GUI/GUI_V6.py1433CODE
LOW9_Firmware/9_3_GUI/GUI_V6.py1453CODE
LOW9_Firmware/9_3_GUI/GUI_V6.py1614CODE
LOW9_Firmware/9_3_GUI/GUI_V6.py1739CODE
LOW9_Firmware/9_3_GUI/GUI_V6.py1765CODE
LOW9_Firmware/9_3_GUI/GUI_V65_Tk.py186CODE
LOW9_Firmware/9_3_GUI/GUI_V65_Tk.py351CODE
LOW9_Firmware/9_3_GUI/GUI_V65_Tk.py1413CODE
LOW9_Firmware/9_3_GUI/GUI_V5.py332CODE
LOW9_Firmware/9_3_GUI/GUI_V5.py1289CODE
LOW9_Firmware/9_3_GUI/GUI_V5.py1388CODE
LOW9_Firmware/9_3_GUI/GUI_V5.py1414CODE
LOW9_Firmware/9_3_GUI/GUI_V5.py1436CODE
LOW9_Firmware/9_3_GUI/GUI_V5.py1566CODE
LOW9_Firmware/9_3_GUI/v7/dashboard.py1289CODE
LOW9_Firmware/9_3_GUI/v7/hardware.py74CODE
LOW9_Firmware/9_3_GUI/v7/processing.py81CODE
LOW9_Firmware/9_3_GUI/v7/processing.py165CODE
LOW9_Firmware/9_3_GUI/v7/workers.py105CODE
LOW9_Firmware/9_3_GUI/v7/workers.py273CODE
LOW9_Firmware/9_3_GUI/v7/workers.py518CODE
LOW9_Firmware/9_3_GUI/v7/agc_sim.py157CODE
LOW9_Firmware/9_2_FPGA/tb/cosim/fpga_model.py136CODE
LOW9_Firmware/9_2_FPGA/tb/cosim/fpga_model.py413CODE
LOW9_Firmware/9_2_FPGA/tb/cosim/fpga_model.py1000CODE
LOW9_Firmware/9_2_FPGA/tb/cosim/fpga_model.py1260CODE
LOW9_Firmware/9_2_FPGA/tb/cosim/radar_scene.py361CODE
LOW9_Firmware/9_2_FPGA/tb/cosim/radar_scene.py450CODE
LOW9_Firmware/9_2_FPGA/tb/cosim/compare.py415CODE
LOW…rmware/9_2_FPGA/tb/cosim/real_data/golden_reference.py534CODE
LOW…rmware/9_2_FPGA/tb/cosim/real_data/golden_reference.py626CODE
LOW…rmware/9_2_FPGA/tb/cosim/real_data/golden_reference.py824CODE
LOW…rmware/9_2_FPGA/tb/cosim/real_data/golden_reference.py1012CODE
LOW8_Utils/Python/CSV_radar_2.py5CODE
LOW8_Utils/Python/CSV_radar.py5CODE
Modern Structural Boilerplate23 hits · 32 pts
SeverityFileLineSnippetContext
LOW9_Firmware/9_3_GUI/GUI_V6_Demo.py30logger = logging.getLogger(__name__)CODE
LOW9_Firmware/9_3_GUI/GUI_V7_PyQt.py23logger = logging.getLogger(__name__)CODE
LOW9_Firmware/9_3_GUI/GUI_PyQt_Map.py53logger = logging.getLogger(__name__)CODE
LOW9_Firmware/9_3_GUI/v7/__init__.py82__all__ = [ # noqa: RUF022CODE
LOW9_Firmware/9_3_GUI/v7/software_fpga.py103 def set_detect_threshold(self, val: int) -> None:CODE
LOW9_Firmware/9_3_GUI/v7/software_fpga.py106 def set_gain_shift(self, val: int) -> None:CODE
LOW9_Firmware/9_3_GUI/v7/software_fpga.py109 def set_cfar_enable(self, val: bool) -> None:CODE
LOW9_Firmware/9_3_GUI/v7/software_fpga.py112 def set_cfar_guard(self, val: int) -> None:CODE
LOW9_Firmware/9_3_GUI/v7/software_fpga.py115 def set_cfar_train(self, val: int) -> None:CODE
LOW9_Firmware/9_3_GUI/v7/software_fpga.py118 def set_cfar_alpha(self, val: int) -> None:CODE
LOW9_Firmware/9_3_GUI/v7/software_fpga.py121 def set_cfar_mode(self, val: int) -> None:CODE
LOW9_Firmware/9_3_GUI/v7/software_fpga.py124 def set_mti_enable(self, val: bool) -> None:CODE
LOW9_Firmware/9_3_GUI/v7/software_fpga.py127 def set_dc_notch_width(self, val: int) -> None:CODE
LOW9_Firmware/9_3_GUI/v7/software_fpga.py130 def set_agc_enable(self, val: bool) -> None:CODE
LOW9_Firmware/9_3_GUI/v7/dashboard.py74logger = logging.getLogger(__name__)CODE
LOW9_Firmware/9_3_GUI/v7/map_widget.py32logger = logging.getLogger(__name__)CODE
LOW9_Firmware/9_3_GUI/v7/hardware.py37logger = logging.getLogger(__name__)CODE
LOW9_Firmware/9_3_GUI/v7/processing.py35logger = logging.getLogger(__name__)CODE
LOW9_Firmware/9_3_GUI/v7/workers.py41logger = logging.getLogger(__name__)CODE
LOW9_Firmware/9_3_GUI/v7/workers.py474 def set_gps(self, gps: GPSData | None) -> None:CODE
LOW9_Firmware/9_3_GUI/v7/workers.py477 def set_waveform(self, wf) -> None:CODE
LOW9_Firmware/9_3_GUI/v7/workers.py480 def set_loop(self, loop: bool) -> None:CODE
LOW9_Firmware/9_3_GUI/v7/workers.py483 def set_frame_interval(self, ms: int) -> None:CODE
Self-Referential Comments6 hits · 21 pts
SeverityFileLineSnippetContext
MEDIUM9_Firmware/9_3_GUI/GUI_V6_Demo.py5# This file is retained for reference only. Do not use for new development.COMMENT
MEDIUM9_Firmware/9_3_GUI/GUI_V6.py3# This file is retained for reference only. Do not use for new development.COMMENT
MEDIUM8_Utils/Python/RADAR_eq.py16 # Create main containerCOMMENT
MEDIUM8_Utils/Python/RADAR_eq.py56 # Create a canvas with scrollbar for input fieldsCOMMENT
MEDIUM8_Utils/Python/RADAR_eq.py87 # Create a frame for each input rowCOMMENT
MEDIUM8_Utils/Python/RADAR_eq.py162 # Create a frame for each result rowCOMMENT
Cross-File Repetition3 hits · 15 pts
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HIGH9_Firmware/9_3_GUI/GUI_V5_Demo.py0parse binary gps format with pitch angle (30 bytes)STRING
HIGH9_Firmware/9_3_GUI/GUI_V6.py0parse binary gps format with pitch angle (30 bytes)STRING
HIGH9_Firmware/9_3_GUI/GUI_V5.py0parse binary gps format with pitch angle (30 bytes)STRING
Redundant / Tautological Comments8 hits · 10 pts
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LOW9_Firmware/9_3_GUI/GUI_PyQt_Map.py1090 # Check if target is still in rangeCOMMENT
LOW9_Firmware/9_2_FPGA/tb/cosim/validate_mem_files.py187 # Check if this looks like it came from generate_reference_chirp_q15COMMENT
LOW9_Firmware/9_2_FPGA/tb/cosim/validate_mem_files.py236 # Check if bandwidth roughly matches expectedCOMMENT
LOW9_Firmware/9_2_FPGA/tb/cosim/validate_mem_files.py344 # Check if they match (they almost certainly won't based on magnitude analysis)COMMENT
LOW9_Firmware/9_2_FPGA/tb/cosim/radar_scene.py256 # Check if this sample falls within the delayed chirpCOMMENT
LOW9_Firmware/9_2_FPGA/tb/cosim/gen_doppler_golden.py196 # Check if a specific scenario was requestedCOMMENT
LOW8_Utils/Python/LUT.py22# Print values in Verilog-friendly formatCOMMENT
LOW…mulations/Antenna/openems_quartz_slotted_wg_10p5GHz.py23#Set PROFILE to "sanity" first; run and check [mesh] cells: stays reasonable.COMMENT
Excessive Try-Catch Wrapping7 hits · 8 pts
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LOW9_Firmware/9_3_GUI/GUI_V5_Demo.py1422 except Exception as e: # noqa: BLE001CODE
LOW9_Firmware/9_3_GUI/GUI_V6_Demo.py1223 except Exception as e: # noqa: BLE001CODE
LOW9_Firmware/9_3_GUI/radar_protocol.py773 except Exception as e: # noqa: BLE001CODE
LOW9_Firmware/9_3_GUI/GUI_V6.py1820 except Exception as e: # noqa: BLE001CODE
LOW9_Firmware/9_3_GUI/GUI_V65_Tk.py1191 except Exception as exc: # noqa: BLE001CODE
MEDIUM9_Firmware/9_3_GUI/GUI_V65_Tk.py1144def _send_custom(self):CODE
LOW9_Firmware/9_3_GUI/GUI_V5.py1663 except Exception as e: # noqa: BLE001CODE
AI Slop Vocabulary2 hits · 4 pts
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LOW9_Firmware/9_2_FPGA/tb/cosim/gen_multiseg_golden.py186 # Generate per-segment reference chirps (just use known patterns)COMMENT
MEDIUM5_Simulations/Fencing/Via_fencing.py7via_pad_B = 0.45 # robust pad caseCODE
AI Structural Patterns2 hits · 2 pts
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LOW9_Firmware/9_3_GUI/test_GUI_V65_Tk.py124CODE
LOW…ions/DAC_ReconstructionFilter/Generate_ChirpcsvFile.py5CODE
Slop Phrases1 hit · 2 pts
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MEDIUM9_Firmware/9_3_GUI/GUI_PyQt_Map.py1022 """Simulates radar targets for demonstration purposes"""STRING
Example Usage Blocks1 hit · 2 pts
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LOW8_Utils/Python/patch_antenna.py58# Example usageCOMMENT